JK MASTER SLAVE FLIP FLOP

A JK flip flop is a synchronous device that , can be used as a storage element . Flip flops are combination of logic gates. The block diagram of a JK flip flop are given below

The Characteristic table of a JK flip flop is given below

Master Slave Flip Flop

Master slave flip flop is a combination of two flip flops connected in such a way that , when one flip flop is active the other gets deactivated . Master-slave flip flop is designed using two separate flip flops. Out of these, one acts as the master and the other as a slave. The figure of a master-slave J-K flip flop is shown below

Working of Master slave flip flop

Lets say we have a master slave flip flop , whose input are represented by arbitrary input symbols YJ and YK, and out puts are represented by HZERO and HONE

We know that flip flop are edge triggered. How ever in master slave flip flop we have two flip flops . so on positive edge master flip flop get triggered and on rising slave flip flop get triggered

So on positive edge inputs are sensed

And on negative edge , out puts are activated hence giving us out put of circuit

Algorithmic State Machine Chart

The algorithmic state machine SM chart can be divided into three blocks namely the state box, the decision box, and the conditional output box

ASM CHART OF MASTER SLAVE JK FLIP FLOP

Understanding The ASM Chart

Here we will try to solve the ASM chart for a master slave JK Flip Flop. It has four states A, B , C, D

Solving State A

When YJ and YC Both are Zero .

If we look at the of flip flop we will realize that when ever YJ is zero ,no matter what other inputs are, the out put will reamin1 .

When YJ and YC Both =1 .

We know that in master slave flip flop , at one time out put is activated and on another time input is activated . As already discussed

When Clock = 1 , INPUT WILL BE SENSED : NO CHANGE IN OUTPUT

WHEN Clock=2 : OUT PUT WILL BE CHANGED

this case the clock signal is 1 so the input signal will be sensed but output will remain same, as master salve flip flop can only produce output when clock is on negative edge

STATE B

On State B , We already have YJ = 1 . Now we need to check YC . As long as YC= 1 , flip flop will keep on sensing input , but out put will not change ,

However as soon as Clock become zero, we gets output HONE or one

STATE C

At state B , we have out put = 1 : and Clock is also one. So no matter what ever new inputs are given , the input will not be sensed and the output will remain same which is H Zero

State D

At state D we have Clock = 0 so now depending on in put we may have 1 and Zero

Link Paths

Now lets suppose zero represent False condition and 1 represents true condition

Similarly whole table can be created

Flip Flop and Control Units.

Lets say we need to have the behavior of above master slave flip flop in control unit. The Goal is to realize the implementation of Control unit in both firma ware and hardware aspects

Creating Micro Words

We already know that we have four states , so lets name them

Implementation of Code in memory

FIRMWARE IMPLANTATION