Practice Problems

The Format of a double operand instruction of a CPU is

If 12 double operand and 30 single operand instructions must be implemented, and if the op code filed must identify the three groups of n operand instructions ,calculate the total number of no operand instructions that can be implemented

Lets say

n =0 = No Operand

n=1= Single Instructions = 30

n=2=Double Instructions= 12

Total Number of possible Instructions = 2 4=16

Out of these 16 instruction 12 operand will be used to identify double operand instruction

Remaining Instruction =16-12=4

Now for Single operands instructions, we will have space for source data (4 bits), which will not be used in this case. So we can use, the source data 4 bits as part of opcode.

So now we have a situation , where we have 4 codes of op code filed, and 16 codes from source field , This situation can be represented graphically as

So total number of codes available are 64. However we only require 30 code. So we can used only first two reaming code , which can accommodate 32 codes.

No we have left with 2 codes . In the case of no operand instruction the destination field can be used . .

So for no operand data =2 codes x 24×24

A CPU which addresses the data through its 16 registers in one of the 12 different modes is to be designed to support 10 arithmetic instruction, 15 logic instruction , 24 data moving instructions , 6 branch instructions and 5 control type instructions. Of these instructions respectively 20% , 60 %, 50% , 50% and 60 % are either single operand or no operand, and rest are double operand type. What is the minimum size of CPU instruction word

.

Number of registers =6

Modes =12

· For referring to the 6 six registers we need to assign them codes . here 3 bits will enough . As 23 =8

· Hence the Register part of source and destination is of 3 bits .

· We have 12 modes. So we can easily represent them with four bits . As 16 codes can be accommodated, and we only need 12

Determining Op code Size

Instruction Type	Number	Single Operand / No operand	Total Instructions	Double Operand Instruction
Arithmetic	10	20%	2	8
Logic	15	60%	9	6
Data Moving	24	50%	12	12
Branch instructions	6	50%	3	3
Control Type	5	60%	3	2

Total Double Instructions=31 instructions

Writing down bits for op code

Total Instruction word 19 bits.

For a given CPU , the first machine cycle M1 always consists of 4 states , and the remaining machine cycle consists either 3 or 4 states. An instruction cycle consists of a minimum 2 and a maximum of 5 machine cycle .

If CPU clock rate is 50 MHz, calculate

a. The shortest

b. The longest

Instruction execution time, if every memory access introduces one wait state.

Now it is given that every first machine cycle has four states . and the next one can have 4 or 5 states

Diagram showing state cycle

· Clock is 50 Mhz

· T=20ns

M1 is fetching instruction

Every time memory is accessed one wait state is introduced

Shortest Instruction

M1 and M2

M1 4 STATES+ 1 EXTRA STATE

M2 3 STATES

Minimum sates 8 States

Longest States

M1 5 SATES

M2 4 SATE+1 WAIT STATE=5 STATE

M3 4 SATE+1 WAIT STATE=5 STATE

M4 4 SATE+1 WAIT STATE=5 STATE

M5 4 SATE+1 WAIT STATE=5 STATE

MAXIMUM SATE 25 STATES

Time required

Minimum : 3x 20 ns

Maximum: 25x 20ns