LECTURE : RTL (Hardware Point of View)
We have already studied the sequence of machine level. We can now elaborate more, and can try to understand , what is the role of hardware in it. Or in real how a computer does completes a machine cycle.
We know that our CPU and Memory Modules are connected with Bus.
A Instruction fetch normally consists of 4 machine cycles . Each machine cycle needs one clock. Hence The fetch cycle needs four cycle
STEP 1
Lets us say CPU places a address on a address register , which is than transferred to a data bus, The data is received by a decoder in the memory section.
The address is decoded by a decoder, which decodes the address and a memory location is slected .
The selected memory location will contain some instruction , which is now selected with the help of a decoder
Step 2
Now the Control Signal , informs the Memory that the processor wants to read the instruction.
Summarizing
Clock Action
T1 ADDR. BUS <— ADDR (CPU)
T2 CTRL BUS <—RD (CPU)
Step 3
Once the data has been selected and the rad signal has been received by the memory , its loads the instruction (DATA) on data bus
Summarizing
Clock Action
T1 ADDR. BUS <— ADDR (CPU)
T2 CTRL BUS <—RD (CPU)
T3 DATA Bus <—– Data Instruction (Mem)
The data by data bus is loaded by memory , and is received by instruction register
Summarizing
T1 ADDR. BUS <— ADDR (CPU)
T2 CTRL BUS <—RD (CPU)
T3 DATA Bus <—– Data Instruction (Mem)
T4 Instr. Reg <—ß Data Bus
Well if the operand is to be fetched, than the received data will be stored in Data register instead of Instruction Register
Question: We have already mentioned that the CPU and data in general are of same size, what will happen if the size is not same
Let say we have a 16 bit CPU and 8 bit memory. Than it will take two cycles, to fill the processor, before processor can execute.
First published on fatsup.wordpress.com ↗