Wait state

We already have discussed the following diagram

We know that the fetch cycle needs four time cycle.

Question to think about is that what will happen if memory is slow as compared to clock cycle and needs more time instead of one clock signal

We can clearly say that for each activity , we have assigned one period .

Mean for slow memories , we will be needing more clock cycles , so that memory can complete its process (lets say 3 or 4)

The memory will keep on using cycles , until its ready. Once memory is ready it will inform the CPU by sending the ready signal, So the cpu can enter T4 state