HC-SR04 ultrasonic sensor test is a student Basys 3 FPGA project written in Verilog. It uses ultrasonic sensor on JA, 7-segment. Play it free on this site: the simulation runs on your own PC, no FPGA board needed.
How to play
Turn on the switch for continuous measuring (or press btnD once). Move the distance slider. The 7-segment shows the echo time in clock cycles (hex)
What it uses
Verilog · ultrasonic sensor on JA, 7-segment
Source code: github.com/suoglu/HC-SR04
