Tetris is a student Basys 3 FPGA project written in SystemVerilog. It uses buttons, Clocking Wizard 30 MHz + 25.175 MHz, music on JB1/JC1. Play it free on this site: the simulation runs on your own PC, no FPGA board needed.
How to play
Press btnC (Space) first to start! btnL/btnR move, btnU rotates, btnD drops
What it uses
SystemVerilog · buttons, Clocking Wizard 30 MHz + 25.175 MHz, music on JB1/JC1
The repo only has the .xdc of its music test; we add a full .xdc and the clock settings from its README. Several registers mix = and <=; fixed automatically. Random pieces come from an Arduino on JA2-4 in the original (drive those pins from the Pmod panel).
Source code: github.com/deterjan/FPGA-Tetris
